| 发明名称 |
SERIAL/PARALLEL CONVERSION CIRCUIT |
| 摘要 |
PURPOSE:To decrease the number of circuit element and to reduce the circuit scale of a serial/parallel conversion circuit. CONSTITUTION:The n-stage shift registers 23 and 24 successively shift the input signals by a master clock. The selectors 21 and 22 select the input signal in place of the n-i stage outputs of the registers 23 and 23 in a (i0<i<n)-bit parallel output mode and input these signals to the (n-i+1) stage of the registers 23 and 24. A latch circuit 35 latches and outputs the outputs of each stage of the registers 23 and 24 by the clocks obtained by dividing the master clock. |
| 申请公布号 |
JPH06120842(A) |
申请公布日期 |
1994.04.28 |
| 申请号 |
JP19920263678 |
申请日期 |
1992.10.01 |
| 申请人 |
FUJITSU LTD |
发明人 |
ISHIKAWA HIROMI;OTSUKI KAZUYA |
| 分类号 |
H03M9/00;(IPC1-7):H03M9/00 |
主分类号 |
H03M9/00 |
| 代理机构 |
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