发明名称 PHASE LOCKED LOOP CIRCUIT
摘要 PURPOSE:To provide a phase locked loop circuit which secures the synchronization when the phase difference between the input and output signals is equal to 0 deg.. CONSTITUTION:A phase locked loop circuit consists of a changeover switch circuit 4 which switches the input and output signals at each fixed time, a phase comparator 1 which compares the switched signal with a reference signal, an LPF 2 which eliminates the high band frequency and detects the error voltage, a sampling/holding amplifier 5 which amplifies the obtained phase error voltage after sampling and holding it by the input and output signals respectively, a voltage control oscillator 3 which varies the frequency in proportion to the phase error voltage, and a phase shift circuit 6 which produces a phase difference 90 deg. between the input and output signals. In such a constitution, the phase difference between the input and output signals can be synchronized with 0 deg..
申请公布号 JPH06120818(A) 申请公布日期 1994.04.28
申请号 JP19920265987 申请日期 1992.10.05
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 ATAKA NAOKI
分类号 H03L7/08;H03L7/081 主分类号 H03L7/08
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