发明名称 Apparatus for and method of clock timing recovery in a receiver.
摘要 <p>A clock phase signal of each time slot of a TDM signal is stored into a corresponding memory location and a clock phase signal of a subsequent time slot is read from a memory location corresponding to the subsequent time slot for recovering clock pulses. A decoder is synchronized with the clock pulses for decoding an encoded digital signal of each time slot to produce a decoded signal. The error rate of the decoded signal of each time slot is detected and compared with a prescribed value. When the detected error rate is determined to be higher than the prescribed value, the write operation of the memory is disabled to prevent the clock phase signal stored in a memory location corresponding to the decoded signal from being overwritten with a subsequent clock phase signal. <IMAGE></p>
申请公布号 EP0594402(A2) 申请公布日期 1994.04.27
申请号 EP19930308309 申请日期 1993.10.19
申请人 NEC CORPORATION 发明人 SHIGEMOTO, NAOTO
分类号 H04J3/06;H04L7/00;H04L7/04;H04L7/10;H04L25/40;(IPC1-7):H04L7/10 主分类号 H04J3/06
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