Subscriber connecting circuit for a digital time division switching exchange.

摘要

The interface chip (SLIC) of the subscriber connection circuit is divided into a high-voltage chip (HV) and into a low-voltage chip. During times free of activity, the high-voltage chip is switched off. In the low-voltage chip, one of the two supply voltages is supplied via a switch (S, R) which is bypassed with a high resistance. This makes it possible to achieve further reduction in power dissipation during times free of activity without inadmissible voltage displacements occurring at the interface (dS) between low-voltage chip and central control unit (St) because of the second supply voltage which cannot be switched off for reasons of expenditure.