发明名称
摘要 <p>PURPOSE:To prevent malfunction without adversely affecting an action speed by varying a resistance value of a load transistor at the dummy cell memory side in accordance with the potential of a signal input line at the memory cell side of a differential data detecting means. CONSTITUTION:A gate of a load transistor 32 in a comparison potential generator circuit 24 is connected to one signal input line 23 of a differential sensor amplifier 22, and a resistance across a source and drain of an FET32 varies in accordance with the potential of the line 23. When the FET32 is made a P- channel and the potential of the line 23 changes at a high level, the resistance value of the FET32 rises, while the potential of a signal input line 26 drops. On the other hand, when the potential of the line 23 changes at a low level, the potential of the line 26 rises. As a result, a difference between both input potentials of the amplifier 22 is increased, and malfunction due to the fluctuation of a power source can be prevented. Moreover it is unnecessary to increase the amplitude of a potential V1 of the line 23, an acting speed will not speed down.</p>
申请公布号 JPH0632234(B2) 申请公布日期 1994.04.27
申请号 JP19840150199 申请日期 1984.07.19
申请人 TOKYO SHIBAURA ELECTRIC CO 发明人 IWAHASHI HIROSHI
分类号 G11C17/18;G11C17/00;(IPC1-7):G11C17/18 主分类号 G11C17/18
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