Semiconductor memory device having improved bit line arrangement

摘要

A semiconductor memory device includes a memory cell array composed of a plurality of memory cells. The memory cell array includes a plurality of word lines interconnecting the memory cells in the row direction and a plurality of bit line pairs interconnecting the memory cells in the column direction. One end of each bit line pair is connected to a clamping circuit, while the other end of each bit line pair is connected via a column select gate to a read/write circuit. Each bit line pair is bent about centrally in the two-dimensional form of a letter U and the clamping circuit and the column select gate are disposed alternately on one same straight line.