| 摘要 |
A data processing system containing a scalar unit, a vector unit, and a storage. The scalar unit receives scalar instructions and vector instructions, carries out scalar data processing in accordance with the scalar instructions, and transfers the vector instructions to the vector unit. The vector unit receives the vector instructions from the scalar unit, carries out vector data processing in accordance with the vector instructions, and contains a post pending signal generating circuit for generating a post pending signal. The post pending signal is made active when a post instruction is received from the scalar unit and is made inactive when a right to access the storage is obtained for reading or storing a last element read or stored by the vector instructions preceding the post instruction. The scalar unit further contains a wait instruction detecting circuit for detecting a transfer of a wait instruction to the vector unit, and an interlock control circuit for suspending executions of instructions which follow a wait instruction which is detected in the wait instruction detecting circuit and each including an operation to access the storage until the post pending signals changes from active to inactive.
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