| 摘要 |
PURPOSE: To provide a device that generates an output signal, in response to an input signal of a variable input level through a digital signal processing technology, without causing destructive noises between frequency transitions. CONSTITUTION: An input signal enters a delay circuit 16 from a terminal 18, is delayed in the circuit 16 for a one clock period, and the delayed signal is outputted from a terminal 20. The output is divided into two, the one is given to a delay circuit 24, where the signal is further delayed by one clock period and the delayed signal is fed to an adder 38 of a next stage. The other output from the delay circuit 16 enters a multiplier 28, where a multiplierδis multiplied with the signal, and the resulting output is fed to the adder 38. The adder 38 adds the two inputs and provides an output of a sum from a terminal 42 as a sine signal X(n). Part of this output is fed back to the input terminal 18 of the delay circuit 16 through a feedback line 44.
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