| 摘要 |
PURPOSE:To simplify circuit configuration by automatically deciding the upper limit and the lower limit of a lock center period and a lock range even when the clock rate of an input signal is changed. CONSTITUTION:The period of the output signal frequency dividing a standard reproducing clock SRCK to 64 by a 6 bits counter 132 is counted and measured with a master clock MCK by a 9 bits counter 137, and the measured value is regarded as a value K3 showing the center period of the reproducing clock. Further, a constant K1 showing the lower limit period of the lock range is obtained by multiplying the measured value by a lock lower limit period ratio by a multiplier 86M, and the constant K2 showing the upper limit period of the lock range is obtained by multiplying the measured value by a lock upper period ratio by the multiplier 87M. |
