| 摘要 |
<p>PURPOSE:To provide a high reliable watchdog timer which is capable of resetting a system even when an infinite loop state is made in a state passing the routine resetting the counter of a watchdog timer. CONSTITUTION:A watchdog timer 10 is composed of a first counter part 12 outputting a carry-out signal after arbitrary time passes from the time when a counter reset signal is inputted, a second counter part 14 outputting the carry- out signal after time which is different from that of the first counter part 12 passes from the time when the counter reset signal is inputted, a system reset signal output part 16 outputting a system reset signal by the timing by which a timer reset signal is inputted and a counter reset signal output part 18 outputting the counter reset signal by the timing by which the timer reset signal is inputted.</p> |
