| 摘要 |
<p>PURPOSE: To provide the CMOS intermediate potential generating circuit of IC formation which generates a low power intermediate potential from a power supply voltage applied to a device. CONSTITUTION: A potential divider 40 is constituted of serially connected resistances R1 , R2 and R3 Arithmetic amplifiers U1 and U2 respond to a voltage Vout, and this voltage Vout is applied by a serial output stage 46 constituted of P-channel transistors Q3 and Q4 and (n) channel transistors Q5 and Q6 connected between power sources Vcc and Vss. The outputs of the arithmetic amplifiers U1 and U2 are respectively connected with each input gate of the transistors Q1 and Q3, and Q2 and Q6. A switch circuit is formed of inventors U3 and U4 , and a transient phenomenon generated when the output of an intermediate stage 44 is switched between the transistors Q1 and Q2 is absorbed. The output Vout of the output stage 46 is taken out from the connecting point of the transistors Q4 and Q5, and simultaneously feedbacked to a comparing stage 42.</p> |
