| 摘要 |
PURPOSE:To provide a DRAM capable of abating the interference noise between bit lines B and/B in a sense amplifier region as well as enhancing the reliability upon data. CONSTITUTION:A precharging circuit 11, an equalizing circuit 12 and a differential amplifier circuit 14 comprising a sense amplifier are provided in a sense amplifier region. On the other hand, the wirings 25a, 25b impressed with a specific potential are provided between the bit line couplings B and/B in the sense amplifier region. |
