| 摘要 |
PURPOSE:To avoid the hindrance to miniaturization in the case of two reference oscillators, increase in power consumption and interference between both the reference oscillators by utilizing a signal from the reference oscillator so as to form an input signal to be compared given to a PLL synthesizer of a high frequency signal processing section and a frequency signal corresponding to a data transmission speed of a base band signal processing section. CONSTITUTION:A signal of a frequency f0 from a reference oscillator 30 is given to a programmable frequency divider 9, which frequency-divides the frequency f0 to an inter-channel frequency fref at a programmable frequency divider 9 and sent to a phase comparator 10 as a compared input signal. Thus, a signal whose frequency is an integral number of multiple of the inter-channel frequency fref (a multiple of N when the frequency division of a programmable frequency divider 13 based on a control signal from a control section (not shown) is 1/N) is fed to a mixing circuit 5 or 16 and the communication at a designated channel is implemented. Furthermore, a signal from the reference oscillator 30 is frequency-divided by a frequency divider (not shown) and becomes a clock signal whose frequency is a frequency f2 corresponding to the data transfer speed of the base band signal processing section and sent to each section of the base band signal processing section. |
