| 摘要 |
PURPOSE:To secure the overlap allowance between the first, second leading out electrodes and a bit line, a capacitor contact by a method wherein the first, second leading out electrodes connecting to a drain and a source region are provided to be connected to a bit line and an accumulation electrode on an upper layer. CONSTITUTION:The stacked capacitor part of a memory cell is formed of an accumulation electrode 123 connected to the source region 110S of a switching transistor through the intermediary of the second lead-out electrode 116 and an opposite electrode 126 formed through the intermediary of an insulation capacitor film 125. Next, a drain region 110D is connected to a bit line 119a through the intermediary of the first lead- out electrode 115. On the other hand, the first and second lead-out electrodes 115, 116 connecting to the drain source regions 110D, 110S are provided. The first lead-out electrode 115 is connected to the bit line 119a on an oxide film 102 while the second lead-out electrode 116 is connected to right above accumulation electrode 123. In such a constitution, the bit line 119a and the accumulation electrode 123 are structured on different layers. Accordingly, it may be almost needless to consider the registration margin between an element region 127, the bit line 119a and the accumulation electrode 123. |
