VERIFYING METHOD FOR INTEGRATED CIRCUIT MASK PATTERN

摘要

PURPOSE:To provide the verifying method of an integrated circuit mask pattern capable of performing verification in a short processing time by performing an efficient arithmetic operation. CONSTITUTION:The circuit connection information of a first system extracted from the mask pattern and the circuit connection information of a second system extracted from a circuit diagram are compared and collated in order to verify whether the circuit diagram and time mask pattern designed based on the circuit diagram are equivalent or not (S30.) In order to obtain the circuit connection information of the first system, the mask pattern is digitized and inputted (S12) and a cell not requiring the verification is specified (S15.) Then, a circuit connection information extraction processing (S17) is performed only for the outside of the specified cell and the corresponding part of the circuit connection information of the second system is fitted and synthesized for the inside of the specified cell (S18.) By comparing the circuit connection information of the first system and the second system, the verification for the part except the specified cell can be performed.