| 摘要 |
<p>PURPOSE:To provide a superior gate array device, which has little clock skew, exerts hardly the effect of a switching noise and is capable of limiting the number of clock drivers. CONSTITUTION:Cells shown by diagonal lines are cells which require a clock. Generally, there are many cases where the cells, which require the clock, are respectively constituted of a flip-flop and the like. Clock drivers 2a, 2b, 2c and 2d are respectively arranged in roughly the central parts of respective virtual split regions. Clock signals from an input cell 4 are respectively connected to the drivers 2a, 2b, 2c and 2d arranged in these regions split into 4. Moreover, the outputs of these drivers 2a, 2b, 2c and 2d are respectively connected only with a cell 5 to need the clock in the region where each clock driver itself is arranged.</p> |
