| 摘要 |
<p>PURPOSE:To improve the reliability of stored data by judging the effectiveness/ ineffectiveness of data based on the result of monitoring whether the output voltage of a capacitor is lower or higher than the operation limit value of a memory. CONSTITUTION:When VCC is supplied, a RESET 0 signal outputted from the first power source monitoring circuit 51 of a control circuit is active at a prescribed timing and inactive at a prescribed timing. On the other hand, the second power source monitoring circuit 55 of the control circuit monitors the output voltage BVCC of the capacitor to output a discrimination output BVCC-ON/OFF signal discriminating whether the output voltage becomes lower than the operation limit value on the standby mode of SRAM or not. The flip-flop 54 of the control circuit latches the BVCC ON/OFF signal outputted from the second power source monitoring circuit by the rising edge of a RESET 1 signal prepared by a shift register 52 so as to output the output to a microprocessor as a BVCC OK signal.</p> |
