The semi-conductor memory unit has a matrix with rows and columns and a read amplifier in the middle of each column. The read amplifier has two cross- wise coupled driver transistors and a load transistor for each driver transistor.A circuit arrangement is provided so that the gate electrode of each load transistor is coupled with the adjacent side of the column conductor. In one embodiment, a matrix of 128 rows and columns is connected with 7-bit address buffers (12, 14) a pulse generator and an input/output control unit
