发明名称 TEST SYSTEM OF INPUTTOUTPUT CONTROL SYSTEM
摘要 PURPOSE:To make it possible to remove a logical fault in a stage of a trial manufacture test by generating an event, which occurs actually once or twice a month, at every minute by artificially increasing a load to an extreme independently of software by using an artificial channel. CONSTITUTION:When FF16 is reset, a MRQ signal (memory request signal) is sent out. On receiving the MRQ signal, channel controller CHC3 sends a SLCT signl (selective signal) out. After sending the SLCT signal out, CHC3 reads the zero- address area of main memory 1 and when data are ready, a MEND signal (memory access end signal) is sent out to artificial channel 8. On reception of the MEND signal, the contents of counter 13 are increased by one. Since the MRQ signal is rising, CHC3 resends the SLCT signal and MEND signal out. When the value of counter 13 reaches its maximum value, a signal of ''1'' is generated on signal line l1 and the presence of the SLCT signal sets FF16 to change switch 15 over to the clock side, so that counter 13 will operate clocks.
申请公布号 JPS5588148(A) 申请公布日期 1980.07.03
申请号 JP19780162739 申请日期 1978.12.27
申请人 FUJITSU LTD 发明人 SHIMIZU SEIICHI;MURANO HATSUO;SANAKA ISAO
分类号 G06F11/22;G06F11/00;G06F13/00 主分类号 G06F11/22
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