MEMORY STRUCTURE OF CONCURRENT I/O OPERATION AT THE SAME ADDRESS FOR FI-FO

摘要

COSA for FIFO comprising first and second subarray (Subarray 1, Subarray 2) including a plurality of unit memory cells consisting of writing access transistor (TR1), saving capacitor (C) and reading access transistor (TR5), a plurality of writing beat lines (In0 - In7) and a plurality of writing word lines (WWL-0 - WWL-X) connected to each of said unit memory cells and writing column address selecting line, characterized in that the FIFO memory comprises a plurality of data latches saving data input from said writing beat line by SAN signal which is activated at the same time with the writing column address selecting signal and connected to the beat lines (In0 - In7) and a data drive which drives the data latches by said SAN signal to enable concurrent I/O at the same address.