| 摘要 |
The memory core circuit comprises data bus lines, word lines, bit lines, and a memory cell array, a first NAND gate for receiving the output of a Y-decoder and a write enable signal, a second NAND gate for receiving the output of the Y-decoder and an inverted write enable signal, a pull-up device for receiving the output of the first NAND gate and consisting of n-channel MOSFETs, and a Y-transmission gate made up of n-channel MOSFETs and p-channel MOSFETs for receiving the inverted output of the first NAND gate and the output of the second NAND gate, thereby reducing the consumption of power.
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