| 摘要 |
<p>PURPOSE:To prevent a sub synchronizing counter from being locked to a speudo synchronizing pattern shorter than the backward protecting time in a PCM signal by adopting the design that the number of stages for the backward protection of the sub synchronizing counter is increased more than that of a main synchronizing counter. CONSTITUTION:A clock is fed to an M-adic counter 16 and a 6-adic counter 13 and a detection pulse and a backward protection setting signal are fed to a ate circuit section 14. When the frame synchronization is established, the output of a counter 13 is '1'. When the output of the counter 10 is M and the detection pulse is inputted, the output of the counter 13 remains logical '1' to keep the synchronizing state. When no detection pulse is inputted, the output of the counter 13 is '2', which represents the forward protection. In the state of hunting, when the detection pulse is inputted, the output of the counter 10 is '1', the output of the counter 13 is '5', and the state of the backward protection is obtained. When the output of the counter 13 is '5' and the output of the counter 10 is M and the detection pulse is inputted with the backward protection setting signal at logical '1', the output of the counter 13 is '1' and the output of the counter 10 is '1' to set the synchronizing state.</p> |
