| 摘要 |
A pulse accumulator (24) operates in a pulse measurement mode. In the pulse measurement mode, accumulator (24) measured pulse lengths of consecutive high and low input signal pulses in reference to a clock signal. A leading-edge capture circuit (50) asserts a leading-edge pulse to indicate a rising edge of the input signal and a trailing-edge capture circuit (52) asserts a trailing-edge pulse to indicate a falling edge of the input signal. The leading-edge and trailing-edge pulses are logically combined (70) to provide a load signal to enable counter (76) to provide an accumulate value to a buffer register (78). After a predetermined delay (62, 64), each of the leading-edge and trailing-edge pulses are logically combined (66) to provide a clear signal which indicates the input signal has transitioned and counter (76) should be cleared to begin measuring a length of a next pulse.
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