发明名称 Method for powering down a microprocessor embedded within a gate array
摘要 An interface circuit (14) that allows for a flexible three-way interface between a microprocessor (12), an ASIC cell block (16), and the external world has been provided wherein the microprocessor and the ASIC cell block are fabricated within a gate array (10). The interface circuit provides circuitry for each I/O pin (22, 23, 24) of the microprocessor to allow it to readily interface with the customer designed ASIC cell block or external devices via the ASIC I/O pads (20). The interface circuit also allows isolated testing of only the microprocessor, of only the ASIC cell block, or of both the microprocessor and the ASIC cell block. The interface circuit and the microprocessor are fully diffused and fixed-placed within the gate array while the ASIC cell block may be utilized by a customer to design a circuit to perform a customer defined function.
申请公布号 US5304860(A) 申请公布日期 1994.04.19
申请号 US19930135637 申请日期 1993.10.12
申请人 MOTOROLA, INC. 发明人 ASHBY, LAURIN R.;STEININGER, FRANZ
分类号 G06F15/78;H01L21/82;H01L27/118;(IPC1-7):H03K19/177 主分类号 G06F15/78
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