| 摘要 |
In a cache DRAM including a DRAM memory array and a SRAM memory array provided on the same chip, a plurality of pairs of MOS transistors are provided, as block transfer gates, so as to connect bit line pairs in the DRAM memory array and bit line pairs in the SRAM memory array one pair by one pair, and a data transfer amount controlling circuit for controlling the plurality of pairs of MOS transistors, a block including a predetermined number of pairs at a time, is newly provided. Data transfer amount controlling circuit is constructed to simultaneously turn on only pairs of MOS transistors included in blocks of a number in accordance with a predetermined external signal out of the plurality of pairs of MOS transistors. Therefore, the amount of data transferred at a time between the DRAM memory array and the SRAM memory array can be changed by changing the combination of the logical levels of external signals.
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