| 摘要 |
In the prior art, selective epitaxial growth (SEG) of semiconductors, performed typically in rectangular windows penetrating through a masking layer located on a major surface of semiconductor substrate, suffers from unwanted facet formation at the corners of the windows-whereby the desirable planar area available for transistor fabrication is reduced. Such facet formation is suppressed-i.e., the area occupied by unwanted facets is reduced-by adding a relatively small lobe penetrating through the masking layer at each corner of each window prior to performing the SEG, whereby transistor packing density can be increased.
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