发明名称 |
Non-inverting buffer circuit device and semiconductor memory circuit device |
摘要 |
A non-inverting buffer circuit device suited for an input buffer circuit of a semiconductor memory is provided so that the number of logic gate stages can be reduced to realize a high speed operation. The circuit is designed in such a way that an MOS transistor at an input stage drives a bipolar transistor at an output stage to produce an output. An n-channel MOS transistor and a p-channel MOS transistor connected in parallel between the base and the collector of the bipolar transistor are on/off controlled by an inverted signal of the input digital signal and a non-inverted signal thereof, respectively. In another aspect, the input buffer circuit includes an inverted signal outputting circuit, and a non-inverted signal outputting circuit in the set mode the input signal in the non-inverted state and outputting in the reset mode the signal at the prescribed potential. The inverted signal outputting circuit includes a bipolar transistor producing an output signal at its collector potential, a first switching circuit for controlling supply of a collector current to the bipolar transistor, an n-channel MOS transistor, connected in parallel between the base and the collector of the bipolar transistor, for supplying a base current to the bipolar transistor in accordance with the input signal, and a second switching circuit for controlling supply of the base current to the bipolar transistor, wherein the first switching circuit and the second switching circuit are selectively on-off controlled.
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申请公布号 |
US5304868(A) |
申请公布日期 |
1994.04.19 |
申请号 |
US19910783781 |
申请日期 |
1991.10.29 |
申请人 |
HITACHI, LTD.;HITACHI VLSI ENGINEERING CORP. |
发明人 |
YOKOYAMA, YUJI;MIYAZAWA, KAZUYUKI;MIWA, HITOSHI;WADA, SHOJI |
分类号 |
G11C11/409;G11C7/10;G11C8/06;G11C11/417;H03K19/013;H03K19/0175;H03K19/0944;(IPC1-7):H03K19/02;G11C8/00 |
主分类号 |
G11C11/409 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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