发明名称 |
Single phase clock distribution circuit for providing clock signals to multiple chip integrated circuit systems |
摘要 |
A circuit to provide single phase clock signals having controlled clock skew to multiple integrated circuit chips is described. A source of single phase clock signals is supplied to a clock signal distribution tree of each integrated circuit. Phase comparison of signals produced by each clock distribution circuit tree provides a control signal for controlling the delay of a clock signal applied to a respective clock distribution tree. A gating circuit is disclosed which produces, in response to each clock signal produced by the clock distribution trees, an accurately controlled LOAD ENABLE and OUTPUT ENABLE signal.
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申请公布号 |
US5305451(A) |
申请公布日期 |
1994.04.19 |
申请号 |
US19900578035 |
申请日期 |
1990.09.05 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
CHAO, HU H.;CHANG, JUNG H.;SHIH, FENG-HSIEN W. |
分类号 |
G06F1/10;G06F1/12;(IPC1-7):G06F1/04;G06F13/372;H03K17/687 |
主分类号 |
G06F1/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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