| 摘要 |
A non-volatile ferroelectric memory with very slight disruption of the memory contents during a read operation. The ferroelectric capacitors are connected to the row and column control lines through transistor switches. Control logic senses the level of current flowing into the ferroelectric capacitor during a read operation. If the current flow exceeds a threshold, the transistor switches are activated to reverse the polarity of the voltage applied to the ferroelectric capacitor.
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