Complementary MOS semiconductor device

摘要

PCT No. PCT/JP90/01151 Sec. 371 Date May 13, 1991 Sec. 102(e) Date May 13, 1991 PCT Filed Sep. 10, 1990.To improve resistance to latch-up of complementary MOS semiconductor device, a high concentration buried layer (16) of same conduction type as a semiconductor substrate (1) and of concentration higher than the silicon semiconductor substrate is formed under a well region (5) of first conduction type in which MOS transistor of second conduction type is formed and a well region (3) of second conduction type in which MOS transistor of first conduction type is formed. The high concentration buried layer (16) reduces parasitic resistance of the semiconductor substrate (1), suppresses transfer of carrier due to surge or the like applied from outside and inside, and inhibits the parasitic transistors (12)(13) from turning on.