发明名称 METHOD FOR FORMING MASK LAYOUT
摘要 PURPOSE:To form a mask layout capable of compacting a large-scale integrated circuit and capable of suppressing the loss of a chip area by using an ordinary design assist. CONSTITUTION:The graphic data showing the mask layout 11 of an integrated circuit are firstly divided along plural longitudinal lines 13 into plural fragments 11x to 11x+3, the fragments are compacted, all the compacted fragments 11x to 11x+3 are divided into plural fragments 11y to 11y+3 along plural lateral lines 14, the fragments are compacted, and the compacted fragments 11 to 11y+3 are connected. Accordingly, since the fragments are compacted one by one, there is no upper processing limit, and a large-scale mask layout is formed with the existing design assist.
申请公布号 JPH06102659(A) 申请公布日期 1994.04.15
申请号 JP19920253183 申请日期 1992.09.22
申请人 TOSHIBA CORP 发明人 MATSUMOTO NOBU;MORI SHOJIRO
分类号 G03F1/70;G06F17/50;H01L21/027 主分类号 G03F1/70
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