| 摘要 |
PURPOSE:To reduce the danger of erroneous frame synchronization establishment and to finish in a short period of time to establish the frame synchronization by inserting the 1st and 2nd frame synchronization patterns with their bit patterns different with each other into transmission data in turn. CONSTITUTION:A frame bit insertion section 47 synchronizes with the clock from a terminal 11 and inserts frame synchronization patterns A and B from a NAND circuit 46 at the position where the insertion timing signal of the transmission data from a terminal 10 indicates a level H. Thus, the patterns A and B are inserted in turn to the transmission data at one frame period and transmitted from a terminal 48 to a transmission path. Therefore, even when the same bit pattern as the pattern A (or B) is existed and coincided in the part other than frame synchronization pattern insertion position of the transmission data, the same bit pattern as the pattern A (or B) other than the synchronization pattern insertion position of the reception data at the next frame synchronization is discordant with the pattern B (or A). |
