| 摘要 |
<p>PURPOSE:To constitute the matrix multiplying circuit by using unit delay elements which are small in circuit scale. CONSTITUTION:In the figure, (a) is an input terminal and a specific input data group is inputted in series. Then, (e) is an output terminal and a desired output data group is outputted in series. The data inputted from (a) are delayed by one and two cycles through the unit delay elements R11 and R12 and outputted to (b) and (c). A selector signal is inputted to (d) from an unshown control circuit to control a two-input selector 31. Then, (a) is connected to one input of the two-input selector 31 through a complement unit 21 of '2' and (c) is connected directly to the other input. Therefore, an adder calculates (e)=(c)+(b) or (e)=(b)+-1X(a)=(b)-(a) with (d). The adder 41 adds (b) and the output of the two-input selector 31 and outputs the result to (e). Therefore, the desired output data group is obtained in order from (e).</p> |
