发明名称 |
Multiprocessor computer system |
摘要 |
A multistage interconnect network (MIN) capable of supporting massive parallel processing, including point-to-point and multicast communications between processor modules (PMs) which are connected to the input and output ports of the network. The network is built using interconnected switch nodes arranged in 2 logb N stages, wherein b is the number of switch node input/output ports, N is the number of network input/output ports and logb N indicates a ceiling function providing the smallest integer not less than logb N. The additional stages provide additional paths between network input ports and network output ports, thereby enhancing fault tolerance and lessening contention. |
申请公布号 |
US5303383(A) |
申请公布日期 |
1994.04.12 |
申请号 |
US19920900731 |
申请日期 |
1992.08.14 |
申请人 |
NCR CORPORATION |
发明人 |
NECHES, PHILIP M.;MCMILLEN, ROBERT J.;WATSON, M. CAMERON;CHURA, DAVID J. |
分类号 |
G06F13/00;G01J3/06;G06F11/00;G06F11/20;G06F11/22;G06F13/36;G06F15/173;(IPC1-7):G06F13/00 |
主分类号 |
G06F13/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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