Circuit arrangement for automatic gain control

摘要

A circuit arrangement for automatic gain control of NRZ data signals. In this arrangement there is detected with the aid of two comparators whether a logic level in the NRZ data signal produced by a controllable amplifier is exceeded or fallen short of. The signals produced by the comparators are time-averaged with the aid of RC combinations and subjected to a logic AND combination. The signal available at the output of the AND combination is integrated in an integrator stage and transported as a control signal to a set input of the controllable amplifier.