发明名称 |
High-speed comparator logic for wide compares in programmable logic devices |
摘要 |
A programmable gate array comprised of a number of configurable functional blocks. Each configurable functional block has a number (m) of inputs. A global interconnect matrix interconnects the configurable functional blocks. The global interconnect matrix provides for routing any combination of signals entering the matrix to any configurable functional block, up to and including the maximum number (m) of inputs of a configurable functional block. Each configurable functional block includes a product term array connected to the m inputs. The product term array can perform a logical AND of up to m bits. A compare term array is also connected to the m inputs. The compare term array can perform an identity compare of up to m/2 bits. A number n of macro cells are provided in each configurable functional block wherein the number n is less that the number m. An allocation circuit allocates the outputs of the compare term array and the product terms to a macro cell, any compare term being allocable in place of a product term to the macro cell.
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申请公布号 |
US5302865(A) |
申请公布日期 |
1994.04.12 |
申请号 |
US19930017851 |
申请日期 |
1993.02.16 |
申请人 |
INTEL CORPORATION |
发明人 |
STEELE, RANDY C.;VIREDAY, RICHARD P. |
分类号 |
H03K19/177;(IPC1-7):H03K19/173;G06F7/38 |
主分类号 |
H03K19/177 |
代理机构 |
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