| 摘要 |
An n-bit input count value is split into high-order n-1 bits and a low-order one bit so that the overflow signal 3a of the n-1 bit counter 2 for counting the high-order n-1 bits and the output signal 4a which is obtained by delaying the overflow signal 3a by half the cycle of the input clock by means of the delay circuit 4 are switched by the switch circuit 5 according to the low-order bit stored in the 1-bit register 6 to achieve a signal having a minimum decomposition width which is half the cycle of the input clock 7a.
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