| 摘要 |
PURPOSE:To economically log an error status and restart a processor in a halt state by generating a processor reset signal by the other processor and resetting only a flip-flop and a register required for restarting. CONSTITUTION:When the processor 1 happens to enter the halt state, the halt state is broadcasted to the other processor 1 through, for example, a common bus 3 together with the processor number. Each processor 1 once recognizing the processor 1 in the halt state writes specific data in the reset generating register 10 of a processor 1 which currently serves as a master. Thus, the specific data are written and a processor resetting generating circuit 11 generates a processor resetting signal (1) to reset only the reducible flip-flop(FF), stage circuit 12 as a register, and control register 13 which are required to restart the processor 1. |
