RECHARGEABLE LOW-POWER-CONSUMPTION ELECTRICALLY ERASABLE COMPLEMENTARY NONVOLATILE PROGRAMMABLE MEMORY CELL

摘要

PURPOSE: To provide an electrically erasable CMOS nonvolatile programmable memory cell (EE cell) which is capable of dispensing with a complex detection circuit and constituting a PLD. CONSTITUTION: A CMOS inverter 45 is formed of an n-channel MOSFET 20 and a p-channel MOSFET 30, having floating gates 21, 31, respectively. A tunnel condenser 13 connecting with a write line 80 via a pass transistor 82 can supply electric charges or remove electric charges for the floating gate. Further, the floating gate is connected to a control gate 10 via a condenser 11. The floating gate gives nonvolatile electric charges. A CMOS inverter detects the presence or absence of electric charges on the floating gate and supplies a amplified reverse output to an output node 60. The output node 60 is connected with a collation line 70, via a pass transistor 72.