PERFORMANCE IMPROVING METHOD FOR SIMPLIFIED INSTRUCTION-SET PROCESSOR

摘要

PURPOSE: To convert an existing data structure code in an SISC (complicated instruction set) type processor so that this code can be used in a high- performance processor while utilizing advantages of an RISC (simple instruction set) type processor. CONSTITUTION: An RISC CPU 10 uses standard instructions and allows the simplified memory access data width. An instruction set is restricted to register- to-register operations and register load/store operations. Atomic byte write can be executed by a load clock/store condition instruction. In the case of a conditional movement instruction, registers are tested, and contents of a second register are moved to a third register and switching to a short branch is performed if a condition is met. A target of the branch is forecasted and a new instruction is fetched to increase the execution speed. Unused bits are used in standard-sized instructions to determine a hint of the address to be forecasted for jump to a subroutine of a jump instruction.