发明名称 METHOD FOR TESTING FAULT PROCESSING FUNCTION OF RAM
摘要 PURPOSE:To write fault data in an address corresponding to a specified logical address in a required RAM constituting a BAA. CONSTITUTION:At the time of receiving a fault injecting instruction, an instruction control part sets up '1' in both of a fault injecting mode register 49 and a row fixing register 59, sets up a row number specified by the fault injecting instruction in a row setting register 31, issues a logical address specified by the fault injecting instruction in an LAR 2, turns a control signal 55 to a value '0', and asserts a PBAA signal 58 to '1'. Thereby a pair of a valid bit value '1' and a parity bit value '1' are written in a column specified by the logical addresses 2, 1 to 3, 0 of the specified row in the RAM together with real addresses.
申请公布号 JPH0695909(A) 申请公布日期 1994.04.08
申请号 JP19920246732 申请日期 1992.09.16
申请人 HITACHI LTD 发明人 SAWAMOTO HIDEO;HIROSE ZENTARO;TAKADA MITSUO
分类号 G06F11/22 主分类号 G06F11/22
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