发明名称 FIFO MEMORY CONTROLLER
摘要 <p>PURPOSE: To improve the quality of an audio signal and to stably maintain synchronization with a video signal. CONSTITUTION: A difference between the write address and the read address of a memory part 102 is taken in a signal synthesis part SUM, and data occupied quantity information BF is obtained. The information BF is compared in comparison parts C1 and C2 to which upper limit and lower limit thresholds are given. When information becomes beyond the thresholds, namely, when it becomes a value lower than the lower limit threshold, it means that occupied quantity is less. The read address is held only once and reading is repetitively executed. When information becomes a value higher than the upper limit threshold, it means that occupied quantity is much and the write address is held only once. Thus, stable data quantity in a range which is set is always maintained in the memory part 102 and delay time between data input/output becomes stable in the range.</p>
申请公布号 JPH0696574(A) 申请公布日期 1994.04.08
申请号 JP19930162766 申请日期 1993.06.30
申请人 ANPETSUKUSU SYST CORP 发明人 KEISU ERU KURINGAA
分类号 G11B20/10;G06F5/10;G06F5/12;G11C7/00;H04N5/222;H04N5/78;H04N5/907;H04N5/91;H04N5/926;H04N5/937;H04N7/085;H04N7/32;H04N7/52;H04N9/802;(IPC1-7):G11C7/00;H04N5/93 主分类号 G11B20/10
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