发明名称 EXTENDED PROCESSOR BUFFER INTERFACE FOR MULTIPROCESSOR
摘要 <p>PURPOSE: To minimize read of a locked memory location and required participation in it in a multiprocessor. CONSTITUTION: For the purpose of minimizing required participation of an additional processor 22a in maintenance of consistency in the multi-processor and read/write of a loaded memory location, an extended processor buffer interface executes atomic fetch and summing operation and supports interleaved memory banks, which perform the operation of burst mode memory access at a rate of 400M bites, and includes a state machine, which can be switched so as to selectively provide a wait state required to support different memory access timings, and provides an improved serial interface for an external multi- element LED display device.</p>
申请公布号 JPH0696030(A) 申请公布日期 1994.04.08
申请号 JP19930143916 申请日期 1993.06.15
申请人 INTERNATL BUSINESS MACH CORP <IBM> 发明人 DEIBITSUDO JIEIMUZU FUOSUTAA
分类号 G06F15/17;G06F13/16;G06F15/167;(IPC1-7):G06F15/16 主分类号 G06F15/17
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