| 摘要 |
PURPOSE:To shorten the time required for variable length/fixed length conversion processings. CONSTITUTION:Before the next variable length encoded data from an encoding means 50 is set to a register 64, the sum of bit length of the present variable length encoded data and remaining data of the register is compared with fixed bit length by a comparing means 70A, and when the sum is above the fixed bit length, the remaining data is shifted in parallel so that a first control means 70B is put close to the uppermost rank of the register 64, and simultaneously, the variable length encoded data inputted this time is set to the register 64 so as to be continued to its shifted data, and thereafter, fixed length data extending from the uppermost rank of the register 64 to a prescribed bit position is outputted to the outside. As a result of comparison by the comparing means 70A, when the sum is below the fixed bit length, the remaining data is shifted in parallel so that a second control means 70C becomes near the higher rank of the register 64, and simultaneously, the variable length encoded data inputted this time is set to the register 64 so as to be continued to its shifted data. |
