发明名称 PICTURE CODING/DECODING DEVICE
摘要 PURPOSE:To improve the efficiency by allocating a code to a degenerative picture element pattern obtained through reduction conversion. CONSTITUTION:An average value calculation circuit 103 calculates an in-block average value of an input picture signal of one frame, a compression processing circuit 104 applies compression processing of a difference PCM and the result is sent via a multiplexer 112. An average value from the circuit 103 is inputted also to a frame memory 105. The content of the memory 105 is referenced to be converted by a reduction conversion pattern generating circuit 106, and all conversion picture element patterns are generated and written in a pattern memory 107. The conversion picture element pattern stored therein is classified by a pattern classification circuit 108. That is, since similar patterns are degenerated into one pattern, the number of picture element patterns is considerably less. The pattern is written in a memory 110 via a sequencing circuit 109, a picture element pattern of a minimum error is selected by an optimum pattern selection circuit 111 and outputted via the multiplexer 112. Thus, the coding efficiency of a moving picture signal is enhanced.
申请公布号 JPH0698310(A) 申请公布日期 1994.04.08
申请号 JP19920242175 申请日期 1992.09.10
申请人 TOSHIBA CORP 发明人 UENO HIDEYUKI;IDA TAKASHI
分类号 H04N1/415;H04N1/41;H04N7/14;H04N19/103;H04N19/136;H04N19/176;H04N19/192;H04N19/196;H04N19/423;H04N19/46;H04N19/463;H04N19/50;H04N19/503;H04N19/51;H04N19/517;H04N19/59;H04N19/70;H04N19/85;H04N19/90;H04N19/94;H04N21/226;H04N21/235;H04N21/426;H04N21/435 主分类号 H04N1/415
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