发明名称 VARIABLE SYSTEM CLOCK TYPE DIGITAL ELECTRONIC STILL CAMERA
摘要 PURPOSE:To provide a variable system clock type digital electronic still camera which can reduce the noises of quantization caused by the A/D conversion and the signal interference caused between the sensors and then can ensure the high picture quality even at a low illuminance by securing such a circuit constitution that can reduce the clock frequency or can increase the clock cycle even at a low illuminance of an object. CONSTITUTION:The image of an object is inputted to a signal processing circuit 8 via an image pickup system, a CDS circuit 5, an A/D converter 7, etc. A system control CPU 13 decides whether the object has a low illuminance or not according to a fact whether the level of the luminance signal supplied from the circuit 8 is higher than a prescribed level or not. If a low illuminance is confirmed, the system clock outputted from a synchronizing signal/timing signal generating circuit 11 is controlled so that the system clock has the frequency lower than that of an NTSC system. Furthermore a CCD driving circuit 10, the converter 7, and the driving circuit of a liquid crystal display 17 can operate in a normal way in response to the system clock of the low frequency.
申请公布号 JPH0698227(A) 申请公布日期 1994.04.08
申请号 JP19920269255 申请日期 1992.09.11
申请人 KYOCERA CORP 发明人 TAKAHASHI MAKOTO
分类号 H04N5/228;H04N5/232;H04N5/235;H04N5/335;H04N5/341;H04N5/353;H04N5/355;H04N5/357;H04N5/363;H04N5/369;H04N5/372;H04N5/376;H04N5/378;H04N101/00;(IPC1-7):H04N5/228 主分类号 H04N5/228
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