| 摘要 |
PURPOSE:To improve the reliability of a multiplexer including a synchronous frequency dividing circuit or an optical transmission system, etc., and to speed up the transmission rate by constructing the synchronous frequency dividing circuit which can surely and synchronously reset the communication data with no omission. CONSTITUTION:In a synchronous frequency dividing circuit FDC including the master-slave type flip-flop FF1-FF3 which are substantially set in a series form and also receive the common synchronous reset signals FPI through the master latch reset input terminals Rm of each bit, the signal FPI is inputted to the slave latch reset terminal Rs of the FF3 of the final bit, for example, at the same time, the latch PLT holding the logical level right before the output signal QP of the FF3 while the signal FPI is kept at a high level is provided. |
