发明名称 VERFAHREN UND SYSTEM ZUR PRÜFUNG VON SIGNALFEHLERN, DIE DURCH EINE ÜBERTRAGUNGSLEITUNG ÜBERTRAGEN WERDEN.
摘要 PCT No. PCT/JP88/00508 Sec. 371 Date Jul. 14, 1988 Sec. 102(e) Date Jul. 14, 1988 PCT Filed May 26, 1988 PCT Pub. No. WO88/09590 PCT Pub. Date Dec. 1, 1988.Errors occurring in information signals (each including control signals), dummy codes and attribute flags for the information signals and the dummy codes, transferred from a transmitting circuit to a receiving circuit through an interface line, with frames arranged in a serial transfer form are detected by using a cyclic redundancy check (CRC). The dummy codes and attribute flags for the dummy codes are not used in this checking. The re-transmission of signals in the frame resulting from a CRC error generated by the attribute flag for the dummy code changing to that of a control signal in the frame is avoided by: (1) providing, at the transmitting circuit, flags for determining the existence and the number of the control signal in the frame in front of the succeeding frame, and (2) comparing signals, relating to the flags, detected in the receiving circuit with the flags.
申请公布号 DE3888091(D1) 申请公布日期 1994.04.07
申请号 DE19883888091 申请日期 1988.05.26
申请人 FUJITSU LTD., KAWASAKI, KANAGAWA, JP 发明人 OKAMOTO, KOICHI 219, IMAINISHIMACHI, KANAGAWA 211, JP;NISHIMURA, KOUSUKE, KOMAE-SHI TOKYO 201, JP;MIYAZAWA, KAZUYOSHI DAI 2 NAKAHARARYO, NAKAHARA-KU, KAWASAKI-SHI KANAGAWA 211, JP;ENDO, KAZUHIKO, MACHIDA-SHI TOKYO 194, JP;MIKUNI, TAMOTSU, MIDORI-KU, YOKOHAMA-SHI KANAGAWA 227, JP
分类号 B31B1/64;B31B27/00;H03M13/00;H04L1/00 主分类号 B31B1/64
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