| 摘要 |
A circuit automatically changes the gain in a PLL for driving a motor of the type having a motor speed signal that indicates the speed of motor rotation. The circuit includes a phase detector for sensing a phase difference between the motor speed signal and a reference frequency and for producing an output signal of duration proportional to the sensed phase difference. A counter counts clock pulses throughout the duration of the output signal, and a motor driving circuit drives the motor in response to the count reached by the counter. A source of clock pulses provides clock signals at first and second frequencies, the second frequency being lower than the first frequency, and a lock range sense circuit produces a sense signal output that indicates when the PLL is within a predetermined phase difference range. A circuit responsive to the sense signal output selectively applies the first frequency to clock the counter when the PLL is within the predetermined phase difference range, and to apply the second frequency to clock the counter when the PLL is operating outside of the predetermined phase difference range. In a method for automatically changing the gain in a PLL for driving a motor of the type having a motor speed signal that indicates the speed of motor rotation, a signal of duration proportional to a phase difference between a motor speed signal and a reference frequency is produced, and a counter is enabled to count clock pulses during the duration of the signal of duration proportional to the phase difference. The motor is driven at a speed relative to the count of the counter. If the PLL is within a predetermined phase difference range the frequency of clock pulses to the counter is controlled to be at a first frequency within a predetermined phase difference range and if the PLL is outside the predetermined phase difference range, the frequency of clock pulses to the counter is controlled to be at a second frequency, lower than said first frequency. <IMAGE> |
