Microprocessor with cache memory

摘要

A microprocessor which has a plurality of cache memory units with plural ways, a plurality of data buses each having different bus width, and a write way control unit or an address control unit whichever capable of switching the number of ways or entries of these cache memory units in accordance with a bus mode determined by a specified data bus and accessing specific cache memory units, where by switching the number of ways or entries in accordance with the set bus mode the byte number of fetched instructions and data is brought into perfect accord with the data width (line size) of respective cache memory units during any bus mode. This in turn fully eliminates unused region of respective cache memory units to provide the improved efficiency of the use of the entire cache memory units.